Without limiting the scope of the invention, its background is described in connection with polishing a semiconductor wafer, as an example.
Heretofore, in this field, chemical-mechanical polishing of silicon wafers has been performed at various stages of device fabrication for planarizing irregular top surface topography. For example, in the process for fabricating modern semiconductor integrated circuits, it is necessary to form conductive lines or other structures above previously formed structures. Prior structure formation, however, often leaves the top surface topography of the silicon wafer highly irregular, with bumps, areas of unequal elevation, troughs, trenches or other surface irregularities. As a result of these irregularities, deposition of subsequent layers of material could easily result in incomplete coverage, breaks in the deposited material, or voids if it were deposited directly over the aforementioned highly irregular surfaces. If the irregularities are not alleviated at each major processing step, the top surface topography of the surface irregularities will tend to become even more irregular, causing further problems as layers stack up in further processing of the semiconductor structure.
Depending upon the type of material used and their intended purposes, numerous undesirable characteristics are produced when these deposition irregularities occur. Incomplete coverage of an insulating oxide layer can lead to short circuits between metalization layers. Voids can trap air or processing gases, either contaminating further processing steps or simply lowering overall device reliability. Sharp points on conductors can result in unusual, undesirable field effects. In general, processing high density circuits over highly irregular structures can lead to very poor yields and device performance.
Consequently, it is desirable to affect some type of planarization or flattening of integrated circuit structures in order to facilitate the processing of multi-layer integrated circuits and to improve their yield, performance, and reliability. In fact, all of today's high-density integrated circuit fabrication techniques make use of some method of forming planarized structures at critical points in the fabrication process.
Conventionally, the polishing apparatus used to planarize a semiconductor wafer has a turntable, often referred to as a rotating platen, and a top ring which exerts a constant pressure on the turntable. A polishing pad is typically attached to the upper surface of the turntable. The semiconductor wafer to be polished, is placed on the polishing pad and clamped between the top ring and the turntable. The semiconductor wafer is securably fixed to the lower surface of the top ring by wax, a pad or a suction so that the semiconductor wafer can be rotated integrally with the top ring during polishing.
While the turntable is rotated, a metered stream of slurry from a slurry supply is delivered to the upper surface of the polishing pad. Typically, the slurry is a liquid comprising chemicals and an abrasive. For example, slurry chemistry generally consists of a basic solution having a pH of about 11. This alkaline polishing slurry may also contain fine polishing particles such as colloidal silica (SiO.sub.2.)
With the recent rapid progress in semiconductor device integration and the demands for smaller and smaller wiring patterns for interconnections with narrower spaces between these interconnections, it has been found that improved methods for planarizing irregular surface topology are required. Several parameters have been discovered which affect the quality of chemical-mechanical polishing of silicon wafers. Specifically, mechanical factors such as the pressure exerted by the top ring on the turntable and the platen speed as well as chemical factors such as slurry type, slurry pH, slurry additives, slurry temperature, slurry dilution ratio, and slurry volume each contribute to the quality of the finish on a semiconductor wafer surface after chemical-mechanical polishing.
More specifically, it has been discovered that the quality of the finish is related to the pH of the slurry. Therefore, what is needed is a method to maintain the pH as well as the buffer capacity of a siliceous chemical-mechanical silicon polishing slurry which will allow for recycling and reuse of the silicon polishing slurry resulting in both a cost savings and a reduced environmental impact from discarded volumes of polishing slurry.